In the U.S. patent application Ser. No. 299,979 filed Sept. 8, 1981 (assigned to the assignee of the invention disclosed herein) there is disclosed an invention for a machine for placing chip type electronic components on a printed circuit board at a very high rate of speed. This chip assembly system is a high speed random component supply system that utilizes an air conveyor to transport chips, one at a time, from their respective input stations to a placement head that places them onto a printed circuit board.
In this type of chip placement assembly apparatus, a small dot of adhesive is placed on the circuit board between the conductive lands of the board. The placement head positions the component on the adhesive to secure the component between the conductive lands of the boards prior to the wave soldering of the boards. U.S. patent application Ser. No. 441,261 filed Nov. 15, 1982 (assigned to the assignee of the invention disclosed herein) is directed to such an adhesive dispensing mechanism.
In the above-described sequence of operation, errors occurring such as placement of the wrong chip or an electrically defective chip are costly to repair once the printed circuit board is completed. Because chips are difficult to repair once they are soldered to the board and since chips have limited identification marking for inspection purposes, a verification that the proper chip has been selected and that the chip is electrically functional affords a tremendous cost saving in the entire assembly apparatus. Therefore, it is desirable to provide in the chip placement mechanism a means to electrically test the component before the component is placed on the board. This is most conveniently done in the line (or conveyor) which transports the chip from the supply to the placement head. Further, during the testing or verifying sequence, the component must be stopped, and the testing for acceptance or rejection of the component must be done with a minimum of delay in order to meet the speed specifications of all the other mechanisms involved in the chip placement apparatus. In fact, in order to meet the chip placement system speed requirements of 15,000 chips/hour, the chip can only remain at the verifier 60 milliseconds (about 1/16 of a second).